
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   15:37:48 04/20/2012
-- Design Name:   Cyclone
-- Module Name:   C:/Users/Usuario/Documents/My Dropbox/CEU/5/AIC/practica/repositorio/tb_Cyclone.vhd
-- Project Name:  Procesador
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Cyclone
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_Cyclone_vhd IS
END tb_Cyclone_vhd;

ARCHITECTURE behavior OF tb_Cyclone_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT Cyclone
	PORT(
		clki : IN std_logic;
		clri : IN std_logic    
		);
	END COMPONENT;

	--Inputs
	SIGNAL clki :  std_logic := '0';
	SIGNAL clri :  std_logic := '0';

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: Cyclone PORT MAP(
		clki => clki,
		clri => clri
	);
	
	clki <= not(clki) after 25 ns;

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 10000 ns;
		
		clri <= '0';
		
		wait for 100ns;
		
		clri <= '1';
		
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;
